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AN1267 APPLICATION NOTE
Advanced Features of the M50FW040 Firmware Hub
CONTENTS
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INTRODUCTION The new STMicroelectronics M50FW040 Firmware Hub Flash Memory is a 4 Mbit device with additional features that are designed to add flexibility for PC platform designers, while lowering the overall system cost. This technical brief describes the additional features of the M50FW040. The M50FW040 Advanced Features are:
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INTRODUCTION A/A MUX INTERFACE MODE FWH INTERFACE MODE - Hardware Write Protection - Register Based Locking - General Purpose Input Pins - Identification Inputs
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Two Interface Modes: - A/A Mux Interface Mode for bulk programming - FWH Interface Mode for in-system use
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Hardware Write Protect Pins for Block Protection Register Based Block Locking 5 General Purpose Input Pins Capability to cascade multiple devices using Identification Inputs
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CONCLUSIONS
The Logic Diagram of the STMicroelectronics M50FW040 is shown in Figure 1; the memory block addresses are shown in Table 1. Table 1. M50FW040 Memory Block Addresses
Block Number 7 6 5 4 3 2 1 0 Block Size (Kbytes) 64 64 64 64 64 64 64 64 Address Range 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh Block Type Top Block Main Block Main Block Main Block Main Block Main Block Main Block Main Block
September 2000
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Figure 1. M50FW040 Logic Diagram
4 ID0-ID3 5 FGPI0FGPI4 FWH4 CLK IC RP INIT M50FW040
4 FWH0FWH3 WP TBL A0-A10
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8 DQ0-DQ7
RC IC G W RP M50FW040 RB
(a) FWH Interface Mode
(b) A/A Mux Interface Mode
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A/A MUX INTERFACE MODE A/A Mux Interface mode of operation is designed to be compatible with existing flash programming equipment for production line programming. It provides a method for component distributors and motherboard manufacturers to pre-program the Flash before and during the motherboard build process. The A/A Mux mode is not designed to be the primary interface during normal use in PC systems. Normal operations should use the FWH Interface mode of operation. A/A Mux Interface mode is selected by driving the Interface Configuration pin, IC, high. The Interface Configuration pin must be driven during reset or prior to power-up and must not be changed during operation. FWH INTERFACE MODE FWH Interface mode is used for normal operation and for access to the advanced features in the M50FW040. This mode is selected by driving the Interface Configuration pin, IC, low. The Interface Configuration pin has an internal pull-down resistor, so this pin can be left unconnected to select FWH Interface mode. The Interface Configuration pin must be set during reset or prior to power-up and must not be changed during operation. The advanced features detailed in the following sections are only accessible in FWH Interface mode. Hardware Write Protection There are two pins that provide write protect capabilities, Top Block Lock and Write Protect. These pins are designed to provide a hardware write protect mechanism directly to the Flash core. If the state of either of these pins changes during a program, erase, or suspend command, the M50FW040 block protection does not change until after completion of the command in progress. The Top Block Lock pin, TBL, controls write access to the top most block of the Flash array. When held low, Top Block Lock prevents program or block erase operations on the top 64 Kbytes block where critical code can be stored. Motherboard designers can use the Top Block for local PC boot code and remote program load information, which are normally not modified after manufacturing. The Write Protect pin, WP, provides the same function as Top Block Lock but affects all remaining blocks. It can be used in conjunction with Top Block Lock to write protect the entire Flash array. These pins over2/8
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ride the function of the software Lock Registers, which are discussed in the Register Based Locking section that follows. There is no default status register to detect the state of these pins, however motherboard designers can use the General Purpose Input pins, FGPI0-FGPI4, report their state. This is shown in detail in the General Purpose Input Pins section of this application note. Register Based Locking Access to the Flash array is additionally controlled by a Lock Register for each 64 Kbytes block. The M50FW040 register configuration map is shown in Table 2. Each block has its own Lock Register. The default value for all Lock Registers at power up or after reset is 01h (write locked). Three bits within each register control access to the blocks: the Read Lock bit, the Write Lock bit and the Lock Down bit. The independent access for each block provides flexibility for system designers to control access to specific regions of the Flash array. This can be useful for backup copies of critical program code and confidential data that is to be stored away from user access. The significance of the three bits in the Lock Registers is: Read Lock. The block is protected from read access when set. Write Lock. The block is protected from write access when set. Lock Down. Lock Down prevents further set or clear operations to the Lock Register bits when set. Lock Down can only be set by software, it cannot be cleared by software once set. The bit is cleared after power cycle or reset operations. Table 2. M50FW040 Lock Register Configuration Map
Memory Address FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h Register Name 70000h-7FFFFh (Top Block) Lock Register 60000h-6FFFFh Lock Register 50000h-5FFFFh Lock Register 40000h-4FFFFh Lock Register 30000h-3FFFFh Lock Register 20000h-2FFFFh Lock Register 10000h-1FFFFh Lock Register 00000h-0FFFFh Lock Register Default Value 01h 01h 01h 01h 01h 01h 01h 01h Access R/W R/W R/W R/W R/W R/W R/W R/W
The Write Lock bit is sampled at the beginning of the operation and must be set to the desired protection state prior to starting a program or erase operation. The state of the bit should not be changed until the end of the operation. If the state of the Write Lock bit is changed during program or erase suspend, the change will not take effect until the end of the suspended operation. Individual bit settings are shown in Table 3, Lock Register Truth Table.
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Table 3. Lock Register Truth Table
Reserved Bits DQ7-DQ3 Read Lock DQ2 0 0 0 0 00000 1 1 1 1 0 0 1 1 0 1 0 1 04h 05h 06h 07h Read Locked Read and Write Locked Read Locked Down Read and Write Locked Down Lock Down DQ1 0 0 1 1 Write Lock DQ0 0 1 0 1 Hex Value 00h 01h 02h 03h Resulting Block State Full R/W Access Write Locked (default) Locked Open Write Locked Down
Note that the hardware write protection pins (Top Block Lock and Write Protect) take precedence over the software locking registers. When Top Block Lock or Write Protect is active, no write access is allowed to the Flash array regardless of the state of the Lock Register. General Purpose Input Pins The M50FW040 provides 5 General Purpose Input pins which are mapped internally to a register as shown in Figure 2. This is a pass-through register, meaning that the five input pins are mapped internally to the register. The register can be read during boot to determine on board device status. Figure 2. M50FW040 General Purpose Input Register Bit Assignments
FFBC0100h - General Purpose Input Register 7 6 5 4 3 2 1 0
(Reserved)
FGPI0-FGPI4 Inputs
FGPI4 FGPI3 FGPI2 FGPI1 FGPI0
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A simple example of a motherboard implementation is shown in Figure 3. The 5 General Purpose Input pins, FGPI0-FGPI4 are connected to various mother board functions to determine status during pre-boot of the Operating System.
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Figure 3. Example Usage of the General Purpose Input pins FGPI0-FGPI4
VCC Recovery Mode
VCC Secure Mode
VCC TBL State
VCC WP State
VCC WP FGPI4 FGPI3 FGPI2 Lid Detect Switch FGPI1 FGPI0 'Sticky-bit'
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TBL
M50FW040
In this example, the General Purpose Input pin assignments are as follows: FGPI0, Lid Detect Switch. The input is connected to a sticky latch which is set when the system unit top cover has been opened. Upon power-up, the FGPI register is read to determine if a transition has occurred. Removal of the system unit cover can be a security breach, thus the implementation provides another level of secure access. FGPI1, Recovery mode. A jumper on the motherboard could be moved by a user or administrator to clear the contents of NVRAM, and boot the system using the critical code stored in the top block. This is sometimes necessary if the BIOS image gets corrupted - for example after a power outage during a write operation. FGPI2, Secure Mode. By placing the jumper in a desired position, the system passwords can be bypassed. This is useful for a system administrator to access a system when a user has lost or forgotten a password. FGPI3, Top Block Lock Status. Used to monitor the status of the Top Block Lock pin, TBL. FGPI4, Write Protect Status. Used to monitor the status of the Write Protect pin. Identification Inputs The Identification Input pins, ID0-ID3, are used to map the M50FW040 into the system memory map. It is possible to connect up to 16 devices, but this may be limited due to bus loading and BIOS support. Multiple devices can be useful in certain instances, for example if more General Purpose Inputs are required or, possibly, when more Flash Memory is required but a higher density device is not available. The appropriate device is selected and responds when the ID Select, IDSEL, field in the FWH cycle on the Low Pin Count, LPC, bus is compared to the hardware strapping on each devices ID pins.
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Figure 4. Example FWH Cycle showing IDSEL
CLK
FWH4
FWH0-FWH3 Number of clock cycles
START 1
IDSEL 1
ADDR 7
MSIZE 1
TAR 2
SYNC 3
DATA 2
TAR 2 AI03437
The host controller has the ability to select which Firmware Hub array maps into each region of the system address space. In the existing host controller, the 4 Mbyte address map is broken into eight 512 Kbyte segments. Inside the host controller is a 32-bit register which contains the mapping information. Refer to the Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub data sheet for detailed information on the operation of the BIOS Select Register. The BIOS Select Register is programmed by system BIOS. As an example of the mapping function, a system with eight 4 Mbit devices would program the register 01234567h. In this configuration, the top segment would be located in device 0 (always), the next 512 Kbytes segment would be located in device 1, and so on, as shown in Figure 5 and Table 4. Figure 5. Example Usage of ID Select Signals
FWH0-FWH4, CLK
M50FW040 Device #0
M50FW040 Device #1
M50FW040 Device #2
M50FW040 Device #3
M50FW040 Device #4
M50FW040 Device #5
M50FW040 Device #6
M50FW040 Device #7
ID0-ID3 = 0000b
ID0-ID3 = 0001b
ID0-ID3 = 0010b
ID0-ID3 = 0011b
ID0-ID3 = 0100b
ID0-ID3 = 0101b
ID0-ID3 = 0110b
ID0-ID3 = 0111b AI03438
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Table 4. Example System Memory Map
Device Number 0 1 2 3 4 5 6 7 Segment Size 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes Address Range 4 GB to 4GB - 0.5MB 4GB - 0.5MB to 4GB - 1MB 4GB - 1MB to 4GB - 1.5MB 4GB - 1.5MB to 4GB - 2MB 4GB - 2MB to 4GB - 2.5MB 4GB - 2.5MB to 4GB - 3MB 4GB - 3MB to 4GB - 3.5MB 4GB - 3.5MB to 4GB - 4MB
Main Memory Region
0 to 16MB Compatibility Region
CONCLUSION The M50FW040 is a flexible Flash Memory with additional functions that can be useful to motherboard and system designers. The device is scalable, allowing multiple devices to connect together to expand the amount of Flash Memory available. Additional features like General Purpose Inputs add flexibility for system designers. The device also has several locking mechanisms to provide a secure path for system BIOS updates. All of these features make the M50FW040 a desirable device for future BIOS and resident OS implementations.
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If you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address:
ask.memory@st.com
(for general enquiries)
Please remember to include your name, company, location, telephone number and fax number.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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